In recent years, with a trend toward a higher density and a higher degree of integration of semiconductor integrated circuits (LSI) used in electronic equipment, the number of pins of the electrode terminals of an LSI chip has been increased and the pitch thereof has decreased rapidly. For mounting LSI chips on wiring boards, flip chip mounting is used widely in order to decrease a wiring delay.
In the flip chip mounting, solder bumps generally are formed on electrode terminals of a LSI chip, which then are joined to electrodes formed on the wiring board at one time via the foregoing solder bumps.
However, in order to mount a next-generation LSI having over 5000 electrode terminals onto a wiring board, it is necessary that solder bumps corresponding to a narrow pitch of 100 μm or less should be formed on the wiring board, but it is difficult to adapt to it with a current technique for forming solder bumps.
Moreover, since it is necessary to form a large number of solder bumps that correspond to the number of the electrode terminals, the productivity has to be raised by shortening a mounting cycle (tact time) for each chip, along with the reduction in cost.
Conventionally, as a technique for forming solder bumps, plating, screen printing, and the like have been developed. The plating is suitable for a narrow pitch, but has a problem in productivity due to its complicated process. On the other hand, the screen printing has excellent productivity, but is not suitable for narrowing a pitch because of the use of a mask.
In the light of the problems described above, several techniques for forming solder bumps selectively on electrodes of a LSI chip or a wiring board have been developed recently. These techniques not only are suitable for forming fine bumps but also have excellent productivity because they can form the bumps all at one time, and attract attention as techniques that are adaptable to the mounting of the next-generation semiconductor chip on the wiring board.
As one of these techniques, there is the following technique: a solder paste, which is a mixture of solder powder and flux, is applied wholly onto a board whose surface is provided with electrodes, and the board is heated so as to melt the solder powder, whereby solder bumps are formed selectively on the electrodes that have high wettability, without short circuits occurring between adjacent electrodes (see Patent Document 1, for example).
There also is a technique called a super solder method. According to this technique, a paste-like composition (chemical reaction deposition-type solder) that contains an organic acid lead salt and metallic tin as main components is applied wholly onto a wiring board on which electrode terminals are formed, and the wiring board is heated so as to cause a substitution reaction between Pb and Sn, thereby depositing a Pb/Sn alloy selectively on the electrodes of the board (see Patent document 2, for example).
Conventional flip chip mounting further requires the step of injecting a resin called an underfill between the semiconductor chip and the wiring board in order to fix the semiconductor chip on the wiring board, after mounting the semiconductor chip on the wiring board on which solder bumps are formed. Because of this, there also have been problems of an increase in the number of steps and a decrease in a yield.
Then, as a method for establishing an electric connection between electrode terminals of the semiconductor chip and connection terminals of the wiring board, which are opposed to each other, and fixing the semiconductor chip onto the wiring board both at the same time, a flip chip mounting technique using an anisotropic electrically conductive material has been developed. In this technique, by supplying a thermosetting resin containing electrically conductive particles between the wiring board and the semiconductor chip, and then heating and setting the thermosetting resin while applying a pressure to the semiconductor chip at the same time, it is possible to establish the electric connection between the semiconductor chip and the wiring board and fix the semiconductor chip to the wiring board at the same time (for example, see Patent Document 3).
Patent Document 1: JP 2000-94179 A
Patent Document 2: JP 1(1989)-157796 A
Patent Document 3: JP 2000-332055 A